1. Field of the Invention
This invention relates generally to semiconductor circuits and more particularly, it relates to merging of a multiplexer circuit or other logic function circuits to a latch circuit or a flip-flop circuit which is formed as a single gate on an integrated circuit semiconductor chip for high speed operation.
2. Description of the Prior Art
In general, there are many circuit applications in which a multiplexer circuit or other logic function circuits such as AND, NAND, XOR, OR, NOR, etc., are required to be followed by a latch or flip-flop circuit. For example, the data input selected by a multiplexer circuit from different circuits are usually stored in a latch or flip-flop circuit. Typically, this is implemented by the use of two separate and distinct gate circuits. The two gates of the multiplexer circuit and latch circuit of the prior art as shown in FIG. 1(a) and 1(b) are then connected in cascade. These prior art circuits have the disadvantages of increased power consumption and increased number of circuit components and a lower operating speed due to the propagation time delay in using two separate gates.
It would thus be desirable to provide a combination multiplexer circuit or other logic function circuit and a latch or flip-flop circuit which are formed as a single gate on an integrated circuit semiconductor chip, thereby increasing the efficiency and speed of operation.